The TLK2711 is a member of the WizardLink transceiver family of multigigabit transceivers, intended for use

　　

　　in ultrahigh-speed bidirectional point-to-point data transmission systems. The TLK2711 supports an effective

　　

　　serial interface speed of 1.6 Gbps to 2.7 Gbps, providing up to 2.16 Gbps of data bandwidth.

　　

　　The primary application of this chip is to provide very high-speed I/O data channels for point-to-point baseband

　　

　　data transmission over controlled impedance media of approximately 50 Ω. The transmission media can be

　　

　　printed-circuit board, copper cables, or fiber-optic cable. The maximum rate and distance of data transfer is

　　

　　dependent upon the attenuation characteristics of the media and the noise coupling to the environment.

　　

　　This device can also be used to replace parallel data transmission architectures by providing a reduction in the

　　

　　number of traces, connector terminals, and transmit/receive terminals. Parallel data loaded into the transmitter

　　

　　is delivered to the receiver over a serial channel, which can be a coaxial copper cable, a controlled impedance

　　

　　backplane, or an optical link. It is then reconstructed into its original parallel format. It offers significant power

　　

　　and cost savings over parallel solutions, as well as scalability for higher data rates in the future.

　　

　　The TLK2711 performs data conversion parallel-to-serial and serial-to-parallel. The clock extraction functions

　　

　　as a physical layer interface device. The serial transceiver interface operates at a maximum speed of 2.7 Gbps.

　　

　　The transmitter latches 16-bit parallel data at a rate based on the supplied reference clock (TXCLK). The 16-bit

　　

　　parallel data is internally encoded into 20 bits using an 8-bit/10-bit (8b/10b) encoding format. The resulting 20-bit

　　

　　word is then transmitted differentially at 20 times the reference clock (TXCLK) rate. The receiver section

　　

　　performs the serial-to-parallel conversion on the input data, synchronizing the resulting 20-bit wide parallel data

　　

　　to the recovered clock (RXCLK). It then decodes the 20-bit wide data using the 8-bit/10-bit decoding format

　　

　　resulting in 16 bits of parallel data at the receive data terminals (RXD0-15). The outcome is an effective data

　　

　　payload of 2 Gbps to 2.5 Gbps (16 bits data x the frequency).

　　

　　The TLK2711 is provided in two packages options: a 80-pin ball grid array MicroStar Junior package and a

　　

　　64-pin VQFP (RCP) package.

　　

　　The TLK2711 provides an internal loopback capability for self-test purposes. Serial data from the serializer is

　　

　　passed directly to the deserializer, providing the protocol device with a functional self-check of the physical

　　

　　interface.